The present invention relates generally integrated circuit processing methods, and more particularly, to a method of fabricating metallized substrates by forming an etch block layer.
Conventional etch blocking layer materials, such as photoresist materials, for example, are typically removed after etching. The assignee of the present invention has previously developed a method of using an etch blocking organic layer and subsequent wet etch procedure which leaves the etch block layer in place. This invention is disclosed in U.S. patent application Ser. No. 08/119,925, filed Sep. 10, 1993, entitled "Phase Mask Laser Fabrication of Electronic Interconnect Structures".
The invention disclosed in this patent application uses phase mask laser machining to fabricate a high density fine patent feature electrical interconnection structure, such as semiconductor wafers, multichip modules, and microelectro-mechanical devices. The phase mask laser machining procedures delineate metal conductor patterns. The conductor patterns are fabricated using a phase mask laser patterned dielectric layer as a conductor wet etch masking layer, or by subtractively removing metal using holographic phase mask laser micromachining.
Using this invention, a first layer of dielectric material is formed on a substrate, a metal layer is formed on the first layer of dielectric material, and a second layer of dielectric material is formed on the metal layer. A phase mask is disposed above the second layer of dielectric material that has a predefined phase pattern therein defining a metal conductor pattern that corresponds to an interconnect structure. The second layer of dielectric material is then processed using the phase mask to form the interconnect structure. The etch mask formed by the second layer of dielectric material need not be removed after etching of the metal, and is made thin enough to not disturb the overall thickness relationship of the interlayer dielectric layer (an additional deposited dielectric layer), whereby the capacitance of the interlayer dielectric is maintained at its desired value.
However, an overhanging ledge is formed above the metal layer and it is possible that this could cause air entrapment and the formation of potentially damaging blisters when the interlayer dielectric layer is deposited. Accordingly, it is an objective of the present invention to provide for an improved method of forming an etch block layer for use in fabricating metallized integrated circuit substrates, and the like, that eliminates these potential problems.